by simonebrunozzi
1 subcomments
- Great guide!
I think the first "My first RISC-V assembly program" emulator plane should be right at the beginning of the guide. Otherwise, casual readers might think that this is a text-only introduction (despite the word "interactive" in the title).
Will spend more time on it in the coming days. I am quite interested in RISC-V and I think that it might have a bright future ahead.
If any AI expert is reading this now, please use Replit or Lovable or something like that to re-create "Core War" [0] with RISC-V assembly. It would be GREAT.
[0]: https://en.wikipedia.org/wiki/Core_War
- Having learned assembly with the book "Computer Organization And Design" from Patterson and Hennessy, it really shows how much RISC-V takes from MIPS. After all they share some of the people involved in both ISAs and they have learned from the MIPS mistakes (no delay slots!). Basically if you come from a MIPS the assembly is very very similar, as it was my case.
Now that book is also available with a RISC-V edition, which has a very interesting chapter comparing all different RISC ISAs and what they do differently (SH, Alpha, SPARC, PA-RISC, POWER, ARM, ...),...
However I've been exploring AArch64 for some time and I think it has some very interesting ideas too. Maybe not as clean as RISC-V but with very pragmatic design and some choices that make me question if RISC-V was too conservative in its design.
- https://github.com/triilman25/tcp-socket-in-riscv-assembly
I wrote TCP Socket for RISCV by using ISA RV64I. You have to know about linker relaxation and how to using it. Some of reference I have attached there
by cbm-vic-20
2 subcomments
- I think there's an error in the Position Independence section:
start:
auipc a0, 3
addi a0, a0, 4
The text says that this should result in 0x3004; was this example intended to be start:
lui a0, 3
addi a0, a0, 4
- The gods have spoken.
I have reached “intro to assembly” in my C course this week and had decided on RISC-V to bridge the gap that everyone has different CPUs and that x86-64 is a little harder to learn than MIPS32, but MIPS32 isn’t as relevant.
And here’s someone who made my course material for the subject entirely.
Thank you so much.
by liqilin1567
1 subcomments
- I have to praise the interactive style of this content.
As a C/C++ dev, I've always thought assembly was much harder. But this interactive content makes assembly clearer.
- Even if there are not that expensive to implement, I do not use official ABI register names, neither pseudo-instructions (I use a command to generate the code on the side).
Once RISC-V has performant silicon implementations (server/desktop/mobile/embedded), the really hard part will be to move the software stack, mostly closed source applications like video games.
And a very big warning: do NOT abuse an assembler macro-preprocessor or you will lock your code on that very assembler. On my side I have been using a simple C pre-processor to keep the door open for any other assembler, at minimal technical cost.
- > Subtracting from zero is negation. What’s the negative of 0x123?
It is 0xfffffedd.
> Hmm, we get 0xfffffccd.
No, we didn't. The emulator shows 0xfffffedd, and I've checked it manually. The emulator is right.
by crabmusket
2 subcomments
- This really makes me want to try fiddling with some low-level stuff again. I studied mechatronics at uni and programmed microcontrollers in C and assembly, but have gone the webdev direction since then. Does anyone have any trusted quality resources for getting into RISC-V hardware? I'm especially interested in using Rust for this if possible - I've wanted an excuse to learn it in more depth for a while.
by Peteragain
2 subcomments
- RISK-V - you can easily get the hardware:
https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...
by bigprovolone
0 subcomment
- if you're looking for an nice RISCV emulator try RARS https://github.com/TheThirdOne/rars
- This looks great. I like how it starts with a dump of all the instructions we'll be using.
Does anyone know of a complete list, machine readable? e.g.
instructions = [{"name": "lui", "description": "load upper immediate", "args": [...]}, ...]
by doublerabbit
1 subcomments
- Within the basic "123" ASM demo, I get that x10 - Becomes 0x00000123 as we are taking the integer of x0 and applying 123 to end of it but why is the sp (x2) register at 0x40100000?
What is that sp? Is it important? Why isn't that at 0x000000? Why isn't that explained? That's when I get lost.
- Great work! I was wondering about this after trying out Easy6502. It would be nice to have a more visual component like Easy6502 which has a draw buffer and snake game tho :)
- Has anyone seen anything similar to this for x86?
- I like this. Do you have a link to your simulator code? I might borrow for a personal project of mine if it's ok.
- tangent I want to link back to this https://github.com/mortbopet/Ripes
- Nice project. RISC-V tools like this make learning architecture concepts much easier. It’s great to see more hands-on resources that help people move from theory to actual CPU behavior.
Hacker News