- > Using `lea` […] is useful if both of the operands are still needed later on in other calculations (as it leaves them unchanged)
As well as making it possible to preserve the values of both operands, it’s also occasionally useful to use `lea` instead of `add` because it preserves the CPU flags.
- > x86 is unusual in mostly having a maximum of two operands per instruction[2]
Perhaps interesting for those who aren't up to date, the recent APX extension allows 3-operand versions of most of the ALU instructions with a new data destination, so we don't need to use temporary registers - making them more RISC-like.
The downside is they're EVEX encoded, which adds a 4-byte prefix to the instruction. It's still cheaper to use `lea` for an addition, but now we will be able to do things like
or rax, rdx, rcx
https://www.intel.com/content/www/us/en/developer/articles/t...
- This guy is tricking us into learning assembly! Get 'em!!
by miningape
1 subcomments
- Loving this series! I'm currently implementing a z80 emulator (gameboy) and it's my first real introduction to CISC, and is really pushing my assembly / machine code skills - so having these blog posts coming from the "other direction" are really interesting and give me some good context.
I've implemented toy languages and bytecode compilers/vms before but seeing it from a professional perspective is just fascinating.
That being said it was totally unexpected to find out we can use "addresses" for addition on x86.
- As a side note of appreciation, I think that we can't do better than what he did for being transparent that LLM was used but still just for the proof-reading.
by mordechai9000
1 subcomments
- This triggers a vague memory of trying to figure out why my assembler (masm?) was outputting a LEA instead of a MOV. I can't remember why. Maybe LEA was more efficient, or MOV didn't really support the addressing mode and the assembler just quietly fixed it for you.
In any case, I felt slightly betrayed by the assembler for silently outputting something I didn't tell it to.
- The text mentions that it can also do multiplication but doesn't expand on that.
E.g. for x * 5 gcc issues lea eax, [rdi+rdi*4].
- >However, in this case it doesn’t matter; those top bits5 are discarded when the result is written to the 32-bit eax.
>Those top bits should be zero, as the ABI requires it: the compiler relies on this here. Try editing the example above to pass and return longs to compare.
Sorry, I don't understand. How could the compiler both discard the top bits, and also rely on the top bits being zero? If it's discarding the top bits, it won't matter whether the top bits are zero or not, so it's not relying on that.
by dist-epoch
2 subcomments
- Do we really know that LEA is using the hardware memory address computation units? What if the CPU frontend just redirects it to the standard integer add units/execution ports? What if the hardware memory address units use those too?
It would be weird to have 2 sets of different adders.
- > However, in this case it doesn’t matter; those top bits are discarded when the result is written to the 32-bit eax.
Fun (but useless) fact: This being x86, of course there are at least three different ways [1] to encode this instruction: the way it was shown, with an address size override prefix (giving `lea eax, [edi+esi]`), or with both a REX prefix and an address size override prefix (giving `lea rax, [edi+esi]`).
And if you have a segment with base=0 around you can also add in a segment for fun: `lea rax, cs:[edi+esi]`
[1]: not counting redundant prefixes and different ModRMs
- It's still wild to me that "Godbolt" is an actual surname.
- Part of the Advent of Compiler Optimisations https://xania.org/AoCO2025
Loving it so far!
- > Yesterday we saw how compilers zero registers efficiently.
It took several tries to understand zero is a verb
by secondcoming
2 subcomments
- The confusing thing about LEA is that the source operands are within a '[]' block which makes it look like a memory access.
I'd love to know why that is.
I think the calculation is also done during instruction decode rather than on the ALU, but I could be wrong about that.
- This trick is something we teach our students when we do 6809 assembly (mainly as a trick to do addition on the index registers). I had no idea it was used as an optimisation in x86.
- What's the current best resources to learn assembly? So that I can understand output of simple functions. I don't want to learn to write it properly, I just want to be able to understand on what's happening.
- Honestly, x86 is not nearly as CISC as those go. It just has a somewhat developed addressing modes comparing to the utterly anemic "register plus constant offset" one, and you are allowed to fold some load-arithmetic-store combinations into a single instruction. But that's it, no double- or triple-indexing or anything like what VAXen had.
BINOP disp(rd1+rd2 shl #N), rs
vs.
SHL rTMP1, rd2, #N
ADD rTMP1, rTMP1, rd1
LOAD rTMP2, disp(rTMP1)
BINOP rTMP2, rTMP2, rs
STORE disp(rTMP1), rTMP2
And all it really takes to support this is just adding a second (smaller) ALU on your chip to do addressing calculations.
by tony-john12
0 subcomment
- [dead]
by badmonster
1 subcomments
- [flagged]
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