by magicalhippo
4 subcomments
- Will be interesting to see how long this RAM insanity will last. If it doesn't calm down before Zen 6 releases, people like me on older platforms might just have to skip Zen 6 entirely and wait for the AM6 platform.
- I’m sure there are a plethora of technical reasons it’s impractical - but my dream is a big, unified L3 cache across their CCD chiplets. Maybe 256mb in size for the x950 x3d chips.
- I hope for a little more PCIe lanes so I can run 2 gaming VMs on these and upgrade my old Threadripper.
- They should be reintroducing the 3D vcache [0] variants (X) in EPYC, with a higher cache/core ratio, that was present in EPYC4 (e.g. 9684X [1]) they for some reason wasn't available in EPYC5.
Makes a massive difference at high density and utilisation, with the standard cache/core performance can really degrade under load.
[0] https://www.amd.com/en/products/processors/technologies/3d-v...
[1] https://www.amd.com/en/products/processors/server/epyc/4th-g...
- "7 GHz clock speed"
When did the GHz race start again?
- > This increases the maximum core count per chiplet from 8 to 12. Furthermore, it increases the L3 cache per CCX/CCD from 32 MB to 48 MB.
I'd say the amount of L3 is not increased but adapted/scaled to the increased core count, since per each core there is still the same amount of cache available as before.
We get faster cores, so we need to get from 5600 to e.g. 6000 DDR5. Since core count is increased by 50%, we'd need 9000... DDR5^W, well yes, we'd need actually as planed before AM6 and DDR6!
- By the time Zen6 launches, there will already be RVA23 chips in the market.
x86 releases will never again be as interesting.
- Well with the way ram is going my next buy may well land on zen 6/ddr6/pcie6
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