If it’s design-level, and tapeout needs to happen for a given chiplet design, why does the article mention different process nodes? And also, how is this different than any fabs available IP?

Thanks!

Then we can have chiplets.

AMD is pretty famous for multi-chip, but they're only recently starting to do actually advanced integrating like Sea-of-Wires between chips. So far most of their chips have had big hot PHY to send data back & forth, rather than trying to make multiple chips that really can communicate directly with each other.

Interesting days ahead. The computer is on the chip now. A smaller domain of system building, with many of the same trade-offs & design challenges that it took to build a box.