Some comments:

- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?

- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.

Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.

> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).

Certainly:

(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input

(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"

(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output

Fails 1/2 tests

(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\

Ive added this to the HN Arcade! https://hnarcade.com/games/games/mvidia

- wire routing makes most circuits write-only. There's no way to follow the wires once a circuit is completed, it's easier to delete them all and start over.

- some of the later levels seem incomplete, at least as far as test cases: 2.26 Row Buffer you don't actually have to buffer the row to meet the requirements. 2.34 can be completed with a single VDD symbol. 2.37 and 2.38 I expected to have access to components that I had completed previously, but then it turned out neither of them have complete tests so they can be cheesed as well.

- no GPU?

otherwise, looks polished and fills in a nice niche!

- https://www.nand2tetris.org/

- https://nandgame.com/

Some suggestions: - What I miss from NAND Game is the challenge of optimizing for efficiency. You'd build a component and it would let you know if it could be built with fewer NAND gates and you'd try to simplify the circuit. For example, while I did "NAND it" with 4 transistors, I did "The dual" with 5 and given the explanation I got afterwards I could have used one less. - This definitely needs to get better on mobile - The description for the first level using BitLine and BitLineBar (I think that was the Sense Amp?) doesn't really explain what it's supposed to do and I had to deduce it from the truth table.

1) the bug report form is completely broken for me (safari on macos 26): one cannot type spaces there bc the space bar still triggers the execution steps, one cannot paste text into there, and sending the reports always fails.

2) I am now stuck on levels 2.26 and 2.37. I just cannot make sense of the instructions given there. Please clarify them.

Otherwise I really enjoyed playing the game!

all the best

- Made timed minigames optional (e.g. binary tables)

- Added 7 (optional) intro levels to walk through pmos and nmos transistors

- Fixed the bug in the capacitor levels

- Changed editor bg to use dots instead of lines to fix wire confusion

We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.

If anybody can create something similarly interactive, educational and hands-on for microbiology or robotics, I am happy to sponsor your cost.

One thing that would make it even stronger: a brief explanation panel for each level showing what real-world GPU component the puzzle maps to. When I completed the truth tables section, I wanted to know where that pattern shows up in actual silicon.

- Nice idea, though after playing Turing complete, I would like to skip the beginning and move to stuff that makes GPUs different to CPUs. But it's understandable.

- I'm not smart enough to intuit NAND from transistors. I'm also not sure I will be alone in that. It's such a weird difficulty wall.

- Speaking of, the difficulty is all over the place. Though easy mode is appreciated.

- Even with a n key rollover keyboard, I couldn't complete the capacitor refresh level. It seems like it speeds up and certain capacitors already start empty.

- The routing for wires is no good atrocious. Any level with more than 8 components will end up impossible to read.

- It doesn't help that you can't color code or even path wires manually.

- Might be Firefox only, but I had a hard time selecting the connection points.

- Dragging the mouse along the edge should pan. Otherwise you have to drop the connection and zoom.

- I appreciate the added "show solution". But it's not really giving you a solution. It's just a better hint.

- An option to show all tests or at least more tests would get great.

For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.

I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.

I see a difficulty pop up after I click "run tests" but it then gets hidden and doesn't do anything.

This was after selecting intermediate on the truth tables level, then clicking "next level" from there.

it was all reasonably easy to get until you get to the sense amplifier which has an almost complete lack of explanation of why you need the required outputs, it is "clear if already known". i.e. if you've never done any electrical engineering it makes zero sense and is not the sort of thing a software developer could ever figure out with the minimal explanation.

No matter what I do, the clock line in the log stays at 1 during tests.

Also the D latches behave very weirdly.

One note: It isn't immediately obvious that the In/Out nodes can be connected to multiple wires, made the first few rounds harder to work thru.

Well done and keep it up :)

- for the load javascript from that page imposes on CPU. +15 °C in less than 30 seconds. Nothing on the page could justify that.

Edit: Confirmed fixed.

I wish I could get into hardware chip level jobs, I was a wiz in logic gates back in university but for jobs been primarily in systems and embedded, sure you work sometimes on rtos or fpga, but it’s another thing where your whole job is designing that! Unfortunately the jobs in hardware feels like a cult, and they expect you working on some industry specific software that you can’t do/access to unless you are in the industry to start with, kinda a catch 22 situation.

I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.

Also when you give a solution, you probably need an explanation of why that works.

Can't wait till you add the additional coming soon levels.

Your feedback feature seems broken. I tried giving feedback about some basic bugs and it kept saying can't send message.

Please also add a waitlist to notify when you release the additional levels.

Teaching is challenging stuff. You have to step out of your current mindset and think with the mind of someone that sees this stuff for the first time. It is not easy to make things look easy and simple. Specifically, I think you need a lot more exploration about cmos logic, about how one side pulls the output up or the other side pulls the output down but they are never on at the same time, about how they effectively amplify the result so the output does not have to depend on the power of the input, etc. Perhaps you can try to have people design things in NMOS logic than in PMOS logic and then combine the two to make a CMOS design to see how they complement each other.

But I do not want to discourage you. This is a very promising start and you should continue if you have the time.

Also, the timed answers -- are you kidding me? The time is waaay too short. And you fail all if you fail a single answer. Oh what is 0xDE in decimal, all I have to do is multiply 16 by 13 and add 14 to that. In my head in 12 seconds. Also the time is not sufficient for filling out truth tables, especially with a laptop trackpad. I was able to pass the truth tables, but gave up on hexracing.

Ok and here are some more specific issues.

-The wires seem to snap in position in a way that they superimpose each other so it becomes very difficult to see what your circuit is doing.

- truth tables seem to be bugged. If you have more inputs than the gate whose truth table you are looking at, sometimes it will generate a fictitious truth table with extra inputs. Thus, some times i get a NOT truth table that has two inputs.

- the ground element should have its connection circle on the top, not the bottom. I realized that you can rotate by pressing R, but the site does not mention that anywhere.

also it kept showing the same table to me like 4 times