- Loved the details about how memory access actually maps addresses to channels, ranks, blocks and whatever, this is rarely discussed.
Not sure how this works for larger data structures, but my first thought was that this should be implemented as some microcode or instruction.
Most computation is not thaat jitter sensitive, perception is not really in the nano to microsecond scale, but maybe a cool gadget for like dtrace or interrupt handers etc.
by shaicoleman
0 subcomment
- * Announcement [1]
* Video [2]
1. https://x.com/lauriewired/status/2041566601426956391 (https://xcancel.com/lauriewired/status/2041566601426956391)
2. https://www.youtube.com/watch?v=KKbgulTp3FE
by 6keZbCECT2uB
0 subcomment
- I like the project: taking it from refresh-induced tail latency to racing threads assigned to addresses that are de-correlated by memory channel. Connecting this to a lookup table which is broadcasted across memory channels to let the lookup paths race makes for a nice narrative, but framing this as reducing tail latency confused me because I was expecting this to do a join where a single reader gets the faster of the two racers.
From a narrative standpoint, I agree it makes more sense to focus on a duplicated lookup table and fastest wins, however, from an engineering standpoint, framing it in terms of channel de-correlated reads has more possibilities. For example, if you need to evaluate multiple parallel ML models to get a result then by intentionally partitioning your models by channel you could ensure that a model does reads on only fast data or only slow data. ML models might not be that interesting since they are good candidates for being resident in L3.
by beached_whale
1 subcomments
- I wonder if there will be a hardware solution in the future that duplicates memory over multiple channels and gives the first result back transparently without threads and racing.
- @lauriewired, I think the most interesting thing that I learned from this is that memory refresh causes readwrite stalls. For some reason I thought it was completely asynchronous.
But otherwise, nice work tying all the concepts together. You might want to get some better model trains though.
by TeapotNotKettle
1 subcomments
- Very interesting work.
But practically speaking, in a real application - isn’t any performance benefit going to be lost by the reduced cache hit rate caused by having a larger working set?
Or are the reads of all-but-one of the replicas non-cached?
Apologies if I am missing something.
- This addresses the “short long tail” (known bounded variance due to the multiple physical operations underlying a single logical memory op), but for hard real time applications the “long long tail” of correctable-ECC-error—and-scrub may be the critical case.
- Kudos... Wonderful work that I think has real value in certain situations... Thanks for sharing!
by jagged-chisel
1 subcomments
- My understanding is that this is making a trade off of using more space to get shorter access times. Do I have that right?
OT: Tail Slayer. Not Tails Layer. My brain took longer to parse that than I’d have wanted.
- [flagged]
Hacker News