1: https://baltazarstudios.com/calculator-introduction/

1. https://git.sr.ht/~twentyafterfour/macro-calculator

Blog post 6 had an error where the picture of a HP-71B (I have one and used its Forth/Assembler ROM manual to write the first HP-48 ROM decoder) where the caption says it is a 48GX (both used a Saturn CPU).

https://baltazarstudios.com/files/calculator-d/Calculator.ht...

https://baltazarstudios.com/files/calculator/Calculator.html

This WebAsm code is compiled using Qt and Verilator so it runs the "hardware" and its microcode inside the simple UI shell that provides the calc interface. In the debug version you can list the ucode, set breakpoints, see regs etc.

Really hoping that ghidra can add support for non-byte aligned memory regions some day. So many cool 4-bit architectures out there and attempting to shoehorn them into ghidra produces not great results

are there videos available?

Also, let us all hate on denomals! :)

The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.

What the project covers:

- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a FAULT state for microcode debugging

- CORDIC for trig functions, verified to 14 significant digits

- Two-pass assembler in Python (~700 lines)

- Verilator + Qt framework: same Verilog source runs in simulation, as a desktop GUI debugger, as WebAssembly, and on real hardware

- Scripting language on top of the microcode for adding functions without touching hardware

- Custom PCB (EasyEDA/JLCPCB), battery, charging circuit

Write-up: https://baltazarstudios.com

Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the...