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RISC-V and Floating-Point

65 points by hasheddan

by Netch

6 subcomments

From a bystanderʼs POV it is excessively hard to memorize all the mess with multiple different extensions. The naming style doesnʼt alleviate the task. But this is a typical issue in the whole RISC-V ecosystem.
What Iʼm slightly confused for is that all these extensions, useful for a minor part of applications, arenʼt moved to longer instructions (6-byte).

by taraharris

1 subcomments

I think it's a good thing to not bake IEEE 754 too deeply into RISC-V.
I really want to see hardware built around posits. This is not because they're necessarily superior to floats (they aren't in all use cases), but just because we need some diversity. Too much standardization is bad for innovation, and not everything that's settled should remain that way.
https://www.sigarch.org/posit-a-potential-replacement-for-ie...

by NooneAtAll3

1 subcomments

looks like there's no mention of soft-floats support, like in Hazard3 cores
see f.e.: https://wren.wtf/shower-thoughts/marks-magic-multiply/

by mavdol04

0 subcomment

Working on a RISC-V emulator targeting Wasm. Is RVV 1.0 stable enough to be worth implementing, or would Zve32f/Zve64d already cover most use cases ?

by andrepd

2 subcomments

Some of the complexity that comes with this really comes from the complexity of IEEE734 itself, plus the fragmentation of alternatives at lower precision.
I would have loved if the article mentioned the efforts at integrating Posits [0] in risc-v. While IEEE734 compatibility will obviously be necessary for any foreseeable future, it would be nice if the industry could settle on a better alternative which avoids many of the flaws with IEEE floats.
[0] https://github.com/andrepd/posit-rust