Considering how slow FPGA are, compared to ASICs, I wonder why multi-phase clocks aren't more common. It really allowed early processors, like the 8088 and 6502, to get a lot more out of the silicon technology of the time. If the design tools supported them better, working with DDR timing would be trivial.
by bschwindHN
0 subcomment
I'm only halfway through but it's refreshing to see such technical articles on HN. Can't claim I'm very knowledgeable in hardware description languages either, but I do light embedded work sometimes and it's really interesting to see how the nitty gritty hardware peripherals and their clocks actually get implemented.
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