by tasty_freeze
2 subcomments
- Northstar made an S-100 card which did FP math, using BCD arithmetic. It had a ucode ROM and a 4b (single digit) ALU, and a few small RAMs to hold the digits. If I remember correctly you could program it to select how many digits you wanted in your representation, up to 14 digits. It did everything one digit at a time, and it had a 256 byte ROM to carry out any digit*digit product in one cycle. For normalization no data was moved -- just the pointer to the appropriate digit was incremented or decremented.
https://s100computers.com/Hardware%20Folder/NorthStar/FP%20B...
by trollbridge
0 subcomment
- Must…resist…clicking link… I’ve got a lot to today and this is like carefully crafted bait to tie me up for the next 4 hours. :-)
by QuadrupleA
0 subcomment
- Always amazed how spoiled we are with modern hardware! The 8087 was $500 in today's dollars, and delivered around 50 kFLOPS of performance (0.00005 GFLOPS).
A cheap mobile phone CPU+GPU costs the manufacturer maybe $20, and typically does 50 GFLOPS on the CPU and 500+ on the GPU. So 10 million times the performance for 1/25th the cost.
Humbling too how "worthless" all the incredible ingenuity of the 8087 circuits and die designs now is, although I'm sure many of those innovations live on in modern chips.
by SyzygyRhythm
1 subcomments
- Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input.
The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?
- Closely related, 8 days ago, 138 points & 28 comments:
https://news.ycombinator.com/item?id=48519011 (about the 8087's adder)
- It's German for
The
Analysis of the 8087 math coprocessor's fast bit shifter,
The
Hacker News